(1) Field of the Invention
The invention relates to a method of metal deposition in the manufacture of an integrated circuit device, and more particularly, to a method of metal deposition without poison via caused by outgassing from spin-on-glass in the manufacture of an integrated circuit.
(2) Description of the Prior Art
As integrated circuit technology is extended into the deep submicron regime, it is more difficult to fill in high aspect ratio via openings during metallization. A plasma-enhanced chemically vapor deposited (PECVD) silicon oxide, spin-on-glass, PECVD silicon oxide sandwich structure is usually used as the inter-metal dielectric in the manufacture of integrated circuits. During the deposition of higher level metal layers, the outgassing of moisture from the spin-on-glass around the via walls causes poison via; that is, poor step coverage of metal in the vias. This results in connection failure between the metal layers. U.S. Pat. No. 5,003,062 to Yen describes this outgassing problem and some methods to solve the problem. The conventional method for higher metal deposition involves the steps of 1) degassing of the spin-on-glass layer at high temperatures, 2) radio frequency (rf) etching to remove residual polymer and native metal oxide, and 3) metal sputtering. However, during step 1), only the surface layer of the spin-on-glass material is cured. This "dry" layer is then etched off during the subsequent step 2), leaving a new spin-on-glass surface full of moisture ready for the metal deposition. Poison via is inevitable. In addition, the high temperature of rf etching causes device degradation such as threshold voltage shift.